The present invention relates to a process for the fabrication of integrated structures including nonvolatile memory cells with self-aligned silicon layers and associated transistors.
Nonvolatile memory cells, both EPROM and E.sup.2- PROM, are known which include a first and a second layer of polycrystalline silicon superimposed on a monocrystalline silicon substrate having appropriately doped active areas. The first layer of silicon, which is closer to the substrate, constitutes the floating gate of the memory cell while the second layer, which is further from the substrate, constitutes the control gate of said cell. Silicon oxide with dielectric functions is interposed between the two aforesaid layers while gate oxide is interposed between the first polycrystalline silicon layer and the monocrystalline silicon substrate. The two polycrystalline silicon layers may if desired be aligned together, that is, as commonly termed, self-aligned.
Also known is the fabrication technique which calls for formation of the integrated structures with several memory cells side by side with self-aligned layers and associated transistors.
According to said technique as it is presently performed self-alignment of the two polycrystalline silicon layers is secured by subsequent use of two different masks, the first for etching of the second layer and the second for subsequent etching of the first layer. The use of two masks results in cost problems but is also important during etching of the first layer to avoid an undesired digging effect in the doped areas and the resulting damage thereto.
It should also be considered that the present fabrication technique forms a transistor with polycrystalline silicon layer separated from the monocrystalline silicon substrate by the same oxide which performs dielectric functions between the two superimposed layers of memory cells. This involves the employment of an interlayer oxide having characteristics better than necessary but which are indispensable for the transistor, which requires an oxide of good quality.
The object of the present invention is therefore to achieve a fabrication process for nonvolatile memory cells with self-aligned silicon layers and associated transistors which will save one mask and at the same time secure transistors with oxide different from the oxide interposed between the two layers of polycrystalline silicon of the memory cells.